The present invention relates to insulated gate field effect transistors (IGFETs). More particularly, it relates to vertical IGFETs which are substantially planar in structure and which are used in power switching applications.
Vertical IGFETs are so named because they incorporate source and drain electrodes on opposite surfaces of a semiconductor wafer. When a predetermined voltage is applied to a gate electrode, a vertical current flow between the source and drain electrodes is established. The gate electrode is typically insulated from the semiconductor surface by a silicon dioxide layer; such IGFETs being referred to as metal-oxide-semiconductor (MOS) FETs. Conventionally, the insulated gate electrode is disposed on the same semiconductor surface as the source electrode, as disclosed in U.S. Pat. No. 4,145,700, POWER FIELD EFFECT TRANSISTORS, issued Mar. 20, 1979, to C. G. Jambotkar, or it is disposed in a groove in a major semiconductor surface, as disclosed in U.S. Pat. No. 4,145,703, HIGH POWER MOS DEVICE AND FABRICATION METHOD THEREFOR, issued Mar. 20, 1979, to R. A. Blanchard et al.
Vertical IGFETs wherein the gate electrode is disposed on a major semiconductor surface are referred to as planar, vertical IGFETs herein, and are commonly referred to in the semiconductor industry as VDMOS (vertical, double diffused MOS) devices. Grooved, vertical IGFETs are commonly referred to in the semiconductor industry as VMOS devices. Being insulated gate structures, both VMOS and VDMOS devices are typically operated in the enhancement mode, and, being vertical devices, they are commonly used in power switching applications. When the predetermined voltage is applied to the gate electrode, a channel is formed in the semiconductor area immediately beneath the oxide of the insulated gate and provides a path for current flow between the source and drain electrodes. Thus, with a VDMOS device the channel is formed at a major semiconductor surface, and in a VMOS device the channel is formed along the surface of the groove in the major semiconductor surface. In both cases the gate electrode is externally disposed on the semiconductor wafer and therefore necessarily consumes a certain amount of surface area.